1. Field of the Invention
The present invention relates to a rail-to-rail operational amplifier, and more particularly, to a rail-to-rail operational amplifier capable of reducing current consumption by controlling bias of compensation capacitors.
2. Description of the Prior Art
With the advance of semiconductor technologies, operating voltages of integrated circuits become lower and lower. For the design of analog circuits, problems of insufficient input and output common-mode voltage of an operational amplifier often occur, and thus the operational amplifier needs to have a rail-to-rail common-mode input and output range to solve these problems.
Generally, a conventional operational amplifier has a two-stage structure, which includes a first stage amplification circuit (amplification stage), and a second stage output circuit (output stage). The first stage amplification circuit is utilized for increasing current or voltage gain of the operational amplifier, and the second stage output circuit is utilized for driving capacitive or resistive loads connected to the operational amplifier. In addition, since the operational amplifier may suffer loop instability problems, Miller compensation capacitors are commonly used to perform frequency compensation for improving loop stability.
Please refer to FIG. 1, which is a schematic diagram of a conventional operational amplifier 10. The operational amplifier 10 is a rail-to-rail operational amplifier including an amplification stage circuit 11, an output stage circuit 12 and a compensation circuit 13. The operational amplifier 10 receives an input signal via a positive input terminal VP, outputs an amplified signal via an output terminal VOUT and forms a feedback path from the output terminal VOUT to a negative input terminal VN. The amplification stage circuit 11 includes a first differential input pair 110, a second differential input pair 120, a first current mirror 130, a second current mirror 140 and a third current mirror 150. The first differential pair 110 includes a pair of matched NMOS transistors MN1 and MN2 and a current source 11 coupled to sources of the transistors MN1 and MN2, which is utilized for providing quiescent currents of the first differential input pair 110. Similarly, the second differential pair 120 includes a pair of matched PMOS transistors MP1 and MP2 and a current source 12 coupled to sources of the transistors MP1 and MP2, which is utilized for providing quiescent currents of the second differential input pair 120.
The first current mirror 130 and the second current mirror 140 are active loads for the first differential input pair 110 and the second differential input pair 120, respectively. The first current mirror 130 includes PMOS transistors MP3, MP4, MP5 and MP6. The second current mirror 140 includes NMOS transistors MN3, MN4, MN5 and MN6. Gates of the transistors MP5, MP6, MN5 and MN6 are all coupled to a bias VB. The third current mirror 150 is represented as current sources 13 and 14, and is utilized for performing summation of output signals from the first differential input pair 110 and the second differential input pair 120 and outputting the summation result to the output stage circuit 12. Operation of the current mirror is well-known to those skilled in the art and explanation is not given here.
The output stage circuit 12 is a class AB push-pull output circuit including a PMOS transistor MP7 and an NMOS transistor MN7, in which gates of the transistors MP7 and MN7 are respectively coupled to a node E and a node F of the amplification stage circuit 11. The compensation circuit 13 is coupled between the amplification stage circuit 11 and the output stage circuit 12 and includes switches S1-S4 and compensation capacitors CM1 and CM2. The switches S1 and S2 and the compensation capacitor CM1 are coupled to a node A; the switch S1 and the amplification stage circuit 11 are coupled to a node B. The switches S3 and S4 and the compensation capacitor CM2 are coupled to a node C; the switch S3 and the amplification stage circuit 11 are coupled to a node D. In the operational amplifier 10, the compensation capacitors CM1 and CM2 are charged and discharged according to switching of the switches S1-S4, which helps loop stability. When the input signal of the operational amplifier 10 is in a transition state where the voltage of the input signal transits from a high level to a low level and from the low level to the high level, the switches S1 and S3 are turned off and the switches S2 and S4 are turned on such that the amplified signal does not pass through the compensation capacitors CM1 and CM2. On the other hand, when the input signal of the operational amplifier 10 is in a steady state, the switches S1 and S3 are turned on and the switches S2 and S4 are turned off such that the amplified signals pass through the compensation capacitors CM1 and CM2, for performing frequency compensation for improving loop stability.
Please note that, when the input signal is in the transition state, the node A is connected to a power supply terminal VDD and the node C is connected to a ground terminal GND. In this situation, a voltage level of the node A is not equal to a steady state voltage level of the node B, and a voltage level of the node C is not equal to a steady state voltage level of the node D. Therefore, when the input signal is in the steady state and the switches S1 and S3 are turned on, charge sharing occurs between the nodes A and B and between the nodes C and D so that the voltage level of the node B is higher than the normal steady state voltage level and discharging occurs on the node B; and the voltage level of the node D is lower than the normal steady state voltage level and charging occurs on the node D. The discharging occurs on the node B and the charging occurs on the node D increase current consumption of the transistors MP6 and MN6.
From the above, the charging and discharging effects occurring on the nodes B and D when the input signal is in the steady state results in unnecessary current consumption and thereby extends the settling time of the operational amplifier 10. In addition, switching of the switches S1-S4 is controlled by an external circuit, which limits the application of the operational amplifier 10.